With the demand for higher levels of integration in semiconductor chips, such as silicon semiconductor chips, to place more and more circuits in the semiconductor chips, a sizable reduction in the dimensions of the transistor of the integrated circuit is a critical step forward in meeting this demand. This is specially the case with a microprocessor integrated circuit chip of which a large portion of the real estate of the chip is an SRAM. For increased performance of future microprocessor, the storage capacity of the SRAM must increase thereby requiring a larger portion of real estate of the microprocessor.
A 1-bit storage cell in SRAM consists of a simple latch circuit with two stable operating points or nodes. Depending on the preserved state of a two-invertor latch circuit, the bit of data being held in the cell will be interpreted either as a logic "0" or as a logic "1". To access the data in the cell via a bit line, a switch controlled by a corresponding word line carrying a row address selection signal. Two complementary access switches are used to connect the 1-bit SRAM cell to the complementary bit lines. A field effect transistor (FET) SRAM cell consists of two cross-coupled invertors and two access transistors. The load devices may be polysilicon resistors, depletion-type N-type FET, or P-type FETs depending on the type of SRAM cell. Pass gates acting as data access switches are enhancement-type N-type FETs.
Since one form of a field effective transistor (FET) is a thin film transistor (TFT) whose dimensions are smaller than the conventional FET, the unitization of TFT in integrated circuits will reduce the amount of silicon needed to fabricate an equivalent number of circuits with conventional FETs. Further, if the TFT can be fabricated using a vertical portion of the silicon chip in contrast to a lateral portion, even more saving of silicon real estate is realized.